The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Nov. 08, 2007
Applicants:

Andy Wei, Dresden, DE;

Thorsten Kammler, Ottendorf-Okrilla, DE;

Roman Boschke, Dresden, DE;

Casey Scott, Dresden, DE;

Inventors:

Andy Wei, Dresden, DE;

Thorsten Kammler, Ottendorf-Okrilla, DE;

Roman Boschke, Dresden, DE;

Casey Scott, Dresden, DE;

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 29/417 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6659 (2013.01); H01L 21/76264 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/41766 (2013.01); H01L 29/66636 (2013.01); H01L 29/66772 (2013.01); H01L 29/7842 (2013.01); H01L 29/7843 (2013.01); H01L 29/7848 (2013.01); H01L 29/78654 (2013.01); H01L 29/665 (2013.01);
Abstract

By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.


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