The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Feb. 06, 2015
Applicant:

Netspeed Systems, San Jose, CA (US);

Inventors:

Pier Giorgio Raponi, San Jose, CA (US);

Sailesh Kumar, San Jose, CA (US);

Eric Norige, East Lansing, MI (US);

Assignee:

NETSPEED SYSTEMS, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/26 (2006.01);
U.S. Cl.
CPC ...
H04L 43/045 (2013.01); H04L 43/0852 (2013.01); H04L 43/0888 (2013.01);
Abstract

Aspects of the present disclosure are directed to methods, systems, and non-transitory computer readable mediums for selective visualization and performance characterization of one or more transactions/messages or subsets of transaction/message of a System-on-Chip (SoC) and/or Network-on-Chip (NoC), with respect to latency, throughput, packet size, data size, hop-to-hop latency breakdown, load of one or more channels, power states of one or more elements of the NoC system, transaction data, among other like performance attributes.


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Raponi, Pier. (2016). System and method for visualization of noc performance based on simulation output (U.S. Patent No. 9444702). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9444702

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