The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2016
Filed:
Aug. 21, 2014
Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;
Kiyoshi Kato, Atsugi, JP;
Yasuhiko Takemura, Isehara, JP;
Tetsuhiro Tanaka, Atsugi, JP;
Takayuki Inoue, Sagamihara, JP;
Toshihiko Takeuchi, Atsugi, JP;
Yasumasa Yamane, Atsugi, JP;
Shunpei Yamazaki, Setagaya, JP;
Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken, JP;
Abstract
A manufacturing method of a semiconductor device in which the threshold is adjusted is provided. In a semiconductor device including a plurality of transistors arranged in a matrix each including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit that supplies a signal to the gate electrode (e.g., word line driver) is provided with a selection circuit formed of an OR gate, an XOR gate, or the like, whereby potentials of word lines can be simultaneously set higher than potentials of bit lines.