The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2016
Filed:
Sep. 15, 2015
Renesas Electronics Corporation, Tokyo, JP;
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Abstract
In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.