The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Jul. 12, 2013
Applicants:

Anis M. Jarrar, Austin, TX (US);

Mark D. Hall, Austin, TX (US);

David R. Tipple, Leander, TX (US);

Surya Veeraraghavan, Austin, TX (US);

Inventors:

Anis M. Jarrar, Austin, TX (US);

Mark D. Hall, Austin, TX (US);

David R. Tipple, Leander, TX (US);

Surya Veeraraghavan, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H03K 19/094 (2006.01);
U.S. Cl.
CPC ...
H03K 19/094 (2013.01); G06F 17/5068 (2013.01); G06F 2217/84 (2013.01);
Abstract

A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.


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