The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Jan. 07, 2014
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Ralf Otremba, Kaufbeuren, DE;

Josef Höglauer, Heimstetten, DE;

Manfred Schindler, Regensburg, DE;

Johannes Lodermeyer, Regensburg, DE;

Thorsten Scharf, Regensburg, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/495 (2006.01); H01L 23/492 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/492 (2013.01); H01L 23/49517 (2013.01); H01L 23/5389 (2013.01); H01L 24/18 (2013.01); H01L 24/20 (2013.01); H01L 24/36 (2013.01); H01L 24/40 (2013.01); H01L 24/71 (2013.01); H01L 21/4857 (2013.01); H01L 24/34 (2013.01); H01L 24/37 (2013.01); H01L 24/39 (2013.01); H01L 24/77 (2013.01); H01L 24/84 (2013.01); H01L 2224/211 (2013.01); H01L 2224/40225 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor package includes a semiconductor die and a metal clip. In one embodiment, the semiconductor die is embedded in an insulating material and has a first surface facing in a first direction, a second surface facing in a second direction opposite the first direction and an edge extending between the first and second surfaces. The metal clip is embedded in the insulating material above the die and bonded to the second surface of the die. Part of the metal clip extends laterally beyond the edge of the die and vertically in the first direction to provide galvanic redistribution at the second surface of the die. Other embodiments of semiconductor packages are also provided.


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