The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Nov. 08, 2012
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Maud Vinet, Rives sur Fure, FR;

Sylvie Mignot, Slingerlands, NY (US);

Romain Wacquez, Marseilles, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 21/311 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76283 (2013.01); H01L 21/311 (2013.01); H01L 21/76232 (2013.01); H01L 21/84 (2013.01); H01L 29/0649 (2013.01);
Abstract

A method of producing a microelectronic device in a substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer, including: etching a trench through the first semiconductor layer, the first dielectric layer, and a part of the second semiconductor layer, defining one active region, and such that, at the level of the second semiconductor layer, a part of the trench extends under a part of the active region; deposition of one second dielectric layer in the trench; etching the second dielectric layer such that remaining portions of the second dielectric layer forms portions of dielectric material extending under a part of the active region; deposition of a third dielectric layer in the trench such that the trench is filled with the dielectric materials of the second and third dielectric layers and forms an isolation trench.


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