The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Jun. 12, 2013
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Markus Brink, White Plains, NY (US);

Michael A. Guillorn, Yorktown Heights, NY (US);

Sebastian U. Engelmann, New York, NY (US);

Hiroyuki Miyazoe, White Plains, NY (US);

Adam M. Pyzyna, Cortlandt Manor, NY (US);

Jeffrey W. Sleight, Ridgefield, CT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 21/033 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3086 (2013.01); H01L 21/0228 (2013.01); H01L 21/0337 (2013.01); H01L 21/0338 (2013.01); H01L 21/3088 (2013.01); H01L 21/32139 (2013.01); H01L 21/28132 (2013.01);
Abstract

A SIT method includes the following steps. An SIT mandrel material is deposited onto a substrate and formed into a plurality of SIT mandrels. A spacer material is conformally deposited onto the substrate covering a top and sides of each of the SIT mandrels. Atomic Layer Deposition (ALD) is used to deposit the SIT spacer at low temperatures. The spacer material is selected from the group including a metal, a metal oxide, a metal nitride and combinations including at least one of the foregoing materials. The spacer material is removed from all but the sides of each of the SIT mandrels to form SIT sidewall spacers on the sides of each of the SIT mandrels. The SIT mandrels are removed selective to the SIT sidewall spacers revealing a pattern of the SIT sidewall spacers. The pattern of the SIT sidewall spacers is transferred to the underlying stack or substrate.


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