The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Mar. 15, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Harry Barowski, Boeblingen, DE;

Silke Penth, Boeblingen, DE;

Wolfgang Penth, Boeblingen, DE;

Tobias Werner, Boeblingen, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/10 (2006.01); G11C 11/419 (2006.01); G11C 11/418 (2006.01); G11C 8/08 (2006.01); G11C 8/12 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 11/418 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 8/12 (2013.01);
Abstract

An aspect relates to a memory array that includes at least a first and a second six transistor static random access memory cell, and first and second address decoders. The first address decoder comprises a first latch, the second address decoder a second latch. First and second address data paths provide first and second address data to the at least two address decoders. The first latch is electrically conductive connected to the first data path and the second latch is electrically conductive connected to the second data path. The first latch is further electrically conductive connectable to the second data path via a first multiplexer. The first multiplexer and the at least two latches are configured to be selectively operated in a first write mode for a write access or in a read mode for a read access to the memory array.


Find Patent Forward Citations

Loading…