The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Jan. 29, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Yen-Hung Lin, Hsinchu, TW;

Chi Wei Hu, Pingzhen, TW;

Yuan-Te Hou, Hsinchu, TW;

Chung-Hsing Wang, Boashan Township, TW;

Chin-Chou Liu, Jhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/5077 (2013.01); G06F 2217/84 (2013.01);
Abstract

Among other things, one or more systems and techniques for tier based layer modification, such as promotion or demotion, for a design layout are provided herein. A metal scheme describes one or more metal layers of the design layout, which are grouped into a set of tiers based upon resistivity similarity between the metal layers. Wire segments of the design layout are evaluated for promotion to tiers providing improved performance, for demotion to tiers providing decreased performance so that relatively faster routing resources are freed up for other wire segments, or for modification such as widening of wire segments. Via count penalties corresponding to timing delays of additional vias used to reassign wire segments are taken into account during promotion. Routing resource gains associated with reassigning wire segments are taken into account during demotion. In this way, wire segments of the design layout are promoted, demoted, or modified.


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