The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Sep. 06, 2012
Applicants:

Toshihiko Saito, Atsugi, JP;

Atsuo Isobe, Isehara, JP;

Kazuya Hanaoka, Fujisawa, JP;

Junichi Koezuka, Tochigi, JP;

Shinya Sasagawa, Chigasaki, JP;

Motomu Kurata, Isehara, JP;

Akihiro Ishizuka, Sagamihara, JP;

Inventors:

Toshihiko Saito, Atsugi, JP;

Atsuo Isobe, Isehara, JP;

Kazuya Hanaoka, Fujisawa, JP;

Junichi Koezuka, Tochigi, JP;

Shinya Sasagawa, Chigasaki, JP;

Motomu Kurata, Isehara, JP;

Akihiro Ishizuka, Sagamihara, JP;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 21/28 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 27/1225 (2013.01);
Abstract

A miniaturized transistor having high electric characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity are achieved. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, source and drain electrode layers are provided in contact with the oxide semiconductor film and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive film and an interlayer insulating film are stacked to cover the oxide semiconductor film, the sidewall insulating layers, and the gate electrode layer, and the interlayer insulating film and the conductive film over the gate electrode layer are removed by a chemical mechanical polishing method, so that the source and drain electrode layers are formed.


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