The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Oct. 07, 2013
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Stefan Flachowsky, Dresden, DE;

Jan Hoentschel, Dresden, DE;

Roman Boschke, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/517 (2013.01); H01L 21/28088 (2013.01); H01L 21/76805 (2013.01); H01L 21/823828 (2013.01); H01L 21/823835 (2013.01); H01L 29/495 (2013.01); H01L 29/4916 (2013.01); H01L 29/4966 (2013.01); H01L 29/665 (2013.01); H01L 29/78 (2013.01); H01L 29/7833 (2013.01);
Abstract

When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process. Metal silicide is only formed on the source and drain regions. The gate electrode is then contacted by forming an aperture through the gate material, leaving the surface of the gate metal layer exposed.


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