The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Oct. 28, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Phil-ouk Nam, Gyeonggi-do, KR;

Jun-kyu Yang, Seoul, KR;

Hun-hyeong Lim, Gyeonggi-do, KR;

Ki-hyun Hwang, Gyeonggi-do, KR;

Jae-young Ahn, Gyeonggi-do, KR;

Dong-chul Yoo, Gyeonggi-do, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/115 (2006.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/11524 (2013.01); H01L 29/66666 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01); H01L 27/11575 (2013.01);
Abstract

A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel structure extends vertically on a substrate. The first stacked structure includes gate electrodes and first interlayer insulating layers. The gate layers and the first interlayer insulating layers are alternately and vertically stacked on each other. The first stacked structure is disposed on a first sidewall of the first vertical channel structure. The second stacked structure includes first sacrificial layers and second interlayer insulating layers. The first sacrificial layers and the second interlayer insulating layers are alternately and vertically stacked on each other. The second stacked structure is disposed on a second sidewall of the first vertical channel structure. The first sacrificial layers is formed of a polysilicon layer.


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