The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Jan. 03, 2014
Applicant:

Broadcom Corporation, Irvine, CA (US);

Inventors:

Rezaur Rahman Khan, Rancho Santa Margarita, CA (US);

Sam Ziqun Zhao, Irvine, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 21/486 (2013.01); H01L 21/4828 (2013.01); H01L 21/4853 (2013.01); H01L 21/768 (2013.01); H01L 23/48 (2013.01); H01L 23/481 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/528 (2013.01); H01L 2224/13 (2013.01); H01L 2224/73204 (2013.01);
Abstract

Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (IC) packages that include compliant dielectric layers. In a through silicon via interposer or substrate, a compliant dielectric material may be added to a surface of silicon material body to form a compliant dielectric layer. The compliant dielectric layer provides a thermal buffer and a stress buffer for a resulting IC package. The compliant dielectric material may be selected such that the coefficient of thermal expansion of the compliant dielectric material approximately matches the coefficient of thermal expansion of the circuit board on which the IC package is mounted. The compliant dielectric material may be selected such that it has a deformability that is greater than the silicon material body. Multiple sub-layers of compliant dielectric material may be used.


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