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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9431347 B1

PDFFull Text
Date of Patent:
Aug. 30, 2016

Filed:

Jun. 03, 2014

Wiring board and method for manufacturing the same

Applicant:

Ibiden Co., Ltd., Ogaki-shi, JP;

Inventors:

Masatoshi Kunieda, Ogaki, JP;

Makoto Terui, Ogaki, JP;

Asuka Il, Ogaki, JP;

Yoshinori Shizuno, Ogaki, JP;

Assignee:

IBIDEN CO., LTD., Ogaki-shi, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Steven T Sawyer

Int. Cl.
CPC ...
H05K 1/11 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5381 (2013.01); H01L 21/4846 (2013.01); H01L 23/49816 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81192 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and having a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and form a distance between adjacent first and third mounting pads which is greater than a distance between adjacent first mounting pads.

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