The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

May. 02, 2015
Applicant:

Alpha and Omega Semiconductor Incorporated, Sunnyvale, CA (US);

Inventors:

Hamza Yilmaz, Saratoga, CA (US);

Yan Xun Xue, Los Gatos, CA (US);

Jun Lu, San Jose, CA (US);

Peter Wilson, Lathrop, CA (US);

Yan Huo, Shanghai, CN;

Zhiqiang Niu, Santa Clara, CA (US);

Ming-Chen Lu, Shanghai, CN;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01); H01L 21/76 (2006.01); H01L 25/00 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/768 (2013.01); H01L 23/49503 (2013.01); H01L 23/49541 (2013.01); H01L 23/49568 (2013.01); H01L 23/49575 (2013.01); H01L 24/83 (2013.01); H01L 25/0655 (2013.01); H01L 2224/83851 (2013.01);
Abstract

A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.


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