The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Nov. 18, 2014
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Tze Yang Hin, Batu Maung, MY;

Loon Kwang Tan, Kepala Batas, MY;

Chew Ching Lim, Sungai Petani, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 25/00 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 21/563 (2013.01); H01L 21/768 (2013.01); H01L 23/3142 (2013.01); H01L 23/528 (2013.01); H01L 24/11 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 25/50 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16057 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/81801 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/14 (2013.01);
Abstract

An integrated circuit package may include an integrated circuit die and a package substrate having a conductive pad. A conductive pillar is formed on a front surface of the integrated circuit die and directly contacts the conductive pad. Prior to contacting the conductive pad directly, the conductive pillar may be positioned adjacent to the conductive pad such that it is aligned to the conductive pad. The integrated circuit package further includes an interconnect structure that is formed in the package substrate. The interconnect structure may include conductive traces that are electrically connected to the conductive pad and the conductive pillar. An additional integrated circuit die may be mounted on the package substrate. The additional integrated circuit die may couple to the integrated circuit die through the interconnect structure.


Find Patent Forward Citations

Hin, Tze. (2016). Integrated circuit package with solderless interconnection structure (U.S. Patent No. 9425174). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9425174

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…