The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Apr. 21, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yu-Fei Huang, Pleasanton, CA (US);

Ming Xiang Li, San Jose, CA (US);

Edward Wan, Fremont, CA (US);

Jacob Chen, Los Altos, CA (US);

Dun-Nian Yaung, Hsin-Chu, TW;

Cheng-Eng Daniel Chen, Richardson, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/768 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 21/76898 (2013.01); H01L 23/5386 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An interconnect structure and a method of forming the interconnect structure are provided. Two wafers (and/or dies) are bonded together. A multi-via interconnect structure is formed extending from a backside of a first substrate to interconnect structures in the metallization layers on the first integrated circuit and the second integrated circuit. The multi-via interconnect structure may be formed by thinning a first substrate of a first wafer and forming a first opening through the first substrate. A second opening extends from the first opening to a first interconnect structure on the first wafer, and a third opening extends from the first interconnect structure on the first wafer to a second interconnect structure on the second wafer. The first, second, and third openings are filled with a conductive material, thereby forming a multi-via interconnect structure.


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