The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2016
Filed:
Nov. 22, 2013
Altera Corporation, San Jose, CA (US);
Xiaohong Jiang, San Jose, CA (US);
Jianming Huang, San Jose, CA (US);
Hong Shi, San Jose, CA (US);
Jianmin Zhang, Los Gatos, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
An integrated circuit package substrate may include a core layer and dielectric layers formed on top and bottom surfaces of the core layer. Routing traces such as stripline structures may be formed in some of the dielectric layers, whereas plated through hole (PTH) structures may be formed through the core layer. A first pair of PTHs that carry a first differential signal may be orthogonally intertwined with a second pair of PTHs that carry a second differential signal. Solder balls formed at the surface of the package substrate may include a first pair of solder balls that convey a first differential signal that is orthogonally intertwined with respect to a second pair of solder balls that convey a second differential signal. The package substrate may be mounted on a printed circuit board (PCB). Differential PCB vias could use the same BGA orthogonal pattern described above.