The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Apr. 23, 2014
Applicants:

Moon-seung Yang, Hwaseong-si, KR;

Mohammad Rakib Uddin, Hwaseong-si, KR;

Myoung-jae Lee, Hwaseong-si, KR;

Sang-moon Lee, Yongin-si, KR;

Sung-hun Lee, Yongin-si, KR;

Seong-ho Cho, Gwacheon-si, KR;

Inventors:

Moon-seung Yang, Hwaseong-si, KR;

Mohammad Rakib Uddin, Hwaseong-si, KR;

Myoung-jae Lee, Hwaseong-si, KR;

Sang-moon Lee, Yongin-si, KR;

Sung-hun Lee, Yongin-si, KR;

Seong-ho Cho, Gwacheon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/8238 (2006.01); H01L 21/8252 (2006.01); H01L 21/8258 (2006.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8238 (2013.01); H01L 21/8252 (2013.01); H01L 21/8258 (2013.01); H01L 27/0605 (2013.01); H01L 27/092 (2013.01);
Abstract

Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. In the CMOS device, a buffer layer is disposed on a silicon substrate, and a first layer including a group III-V material is disposed on the buffer layer. A second layer including a group IV material is disposed on the buffer layer or the silicon substrate while being spaced apart from the first layer.


Find Patent Forward Citations

Loading…