Three-dimensional memory structure employing air gap isolation

Abstract

Electrically conductive layers for control gate electrodes of a vertical memory device can be vertically spaced by cavities to reduce capacitive coupling between neighboring electrically conductive gate electrodes. An alternating stack of first material layers and second material layers can be provided. After replacing the second material layers with electrically conductive layers, the first material layers can be removed to form cavities between the electrically conductive layers. A dielectric material can be deposited with high anisotropic deposition rate to form an insulating spacer. For example, a plasma assisted atomic layer deposition process can be employed to deposit a dielectric spacer that include laterally protruding portions that encapsulate the cavities at each level between neighboring pairs of electrically conductive layers. A contact via structure can be formed in the insulating spacer to provide electrical contact to a source region.