The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2016
Filed:
Oct. 14, 2014
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Balaji Kannan, Fishkill, NY (US);
Unoh Kwon, Fishkill, NY (US);
Rekha Rajaram, Hopewell Junction, NY (US);
Assignee:
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 27/092 (2006.01); H01L 29/51 (2006.01); H01L 21/8238 (2006.01); H01L 21/225 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/02192 (2013.01); H01L 21/02247 (2013.01); H01L 21/2255 (2013.01); H01L 21/28088 (2013.01); H01L 21/28185 (2013.01); H01L 21/823842 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 21/02252 (2013.01); H01L 21/02255 (2013.01);
Abstract
Embodiments of the present invention provide CMOS structures and methods of gate formation that combine a keep-cap scheme in which a protective layer is maintained on a PFET during a replacement metal gate process that utilizes an NFET-first process flow. Selective nitridation is used to provide nitrogen to the NFET while the PFET is protected from nitrogen by the keep-cap. Additional dopants are provided to the NFET using a gate stack dopant material (GSDM) layer.