The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2016
Filed:
Feb. 02, 2015
Globalfoundries Inc., Grand Cayman, KY;
Yan Ping Shen, Saratoga Springs, NY (US);
Min-hwa Chi, Malta, NY (US);
Xusheng Wu, Ballston Lake, NY (US);
Weihua Tong, Mechanicville, NY (US);
Haiting Wang, Clifton Park, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting Nin the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the Nimplanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.