The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2016

Filed:

Mar. 25, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Keith Alan Bowman, Morrisville, NC (US);

Jeffrey Todd Bridges, Raleigh, NC (US);

Sarthak Raina, Raleigh, NC (US);

Yeshwant Nagaraj Kolla, Wake Forest, NC (US);

Jihoon Jeong, Cary, NC (US);

Francois Ibrahim Atallah, Raleigh, NC (US);

William Robert Flederbach, Holly Springs, NC (US);

Jeffrey Herbert Fischer, Raleigh, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/26 (2006.01); H03K 5/13 (2014.01); G06F 1/10 (2006.01); H03K 5/156 (2006.01); H03K 5/134 (2014.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/13 (2013.01); G06F 1/10 (2013.01); H03K 5/134 (2014.07); H03K 5/156 (2013.01); H03K 2005/00019 (2013.01);
Abstract

Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.


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