The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2016

Filed:

Dec. 19, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Hung-Chang Yu, Hsinchu, TW;

Ying-Hao Kuo, Hsinchu, TW;

Kai-Chun Lin, Hsinchu, TW;

Yue-Der Chih, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/00 (2013.01); H01S 5/30 (2006.01); H04B 10/43 (2013.01); H01S 5/02 (2006.01); H01S 5/026 (2006.01); H01S 5/028 (2006.01); H01S 5/183 (2006.01);
U.S. Cl.
CPC ...
H01S 5/3027 (2013.01); H01S 5/021 (2013.01); H01S 5/026 (2013.01); H01S 5/0261 (2013.01); H04B 10/43 (2013.01); H01S 5/0285 (2013.01); H01S 5/183 (2013.01);
Abstract

A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver. A first serializer/deserializer (SerDes) is connected to the first optical transceiver and a second SerDes is connected to the second optical transceiver. The SerDes converts parallel data input into serial data output including a clock signal that the first transceiver transmits to the second transceiver. The semiconductor arrangement has a lower area penalty than traditional intra-layer communication arrangements that do not use optics for alignment, and mitigates alignment issues associated with conventional techniques.


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