The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2016

Filed:

May. 22, 2014
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Jin Ho Bae, Suwon-si, KR;

Qwan Ho Chung, Seoul, KR;

Seong Kweon Ha, Yangju-si, KR;

Jong Hyun Kim, Seoul, KR;

Bok Gyu Min, Incheon-si, KR;

Jae Won Shin, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/12 (2006.01); H01L 23/498 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 24/85 (2013.01); H01L 21/481 (2013.01); H01L 22/32 (2013.01); H01L 23/12 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01); H01L 2224/85 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/181 (2013.01);
Abstract

A method of manufacturing a semiconductor package includes: forming a strip substrate including a plurality of unit substrates, each being provided with a first connection pad and a second connection pad on a first surface of the unit substrate and each unit substrate being electrically and physically isolated from each other with the intervention of saw lines, first ground connection pads formed on the respective unit substrates, each of the first ground connection pads being electrically coupled with the first connection pad over the respective unit substrates, second ground connection pads formed on the saw line on the first surface side of the unit substrates and electrically isolated from the unit substrates, and test wiring formed on the saw line, the test wiring being electrically isolated from the unit substrates and electrically coupled with the second ground connection pads; and attaching semiconductor chips onto the respective unit substrates.


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