The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Apr. 10, 2015
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Danny Pak-Chum Shum, Poughkeepsie, NY (US);

Yong Wee Francis Poh, Singapore, SG;

Upinder Singh, Singapore, SG;

Yuan Sun, Singapore, SG;

Myo Aung Maung Maung, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42324 (2013.01); H01L 27/11558 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01); H01L 29/7883 (2013.01); H01L 29/7885 (2013.01);
Abstract

Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate prepared with an isolation well, a HV well region and first and second wells disposed in the substrate. The memory cell further includes a first transistor having a select gate and a second transistor having a floating gate adjacent to one another and disposed over the second well. The transistors include first and second diffusion regions disposed adjacent to the sides of the gates. A control gate is disposed over the first well and coupled to the floating gate. The control and floating gates include the same gate layer extending across the first and second wells. The control gate includes a capacitor.


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