The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Jul. 26, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Lisa F. Edge, Watervliet, NY (US);

Hemanth Jagannathan, Guilderland, NY (US);

Balasubramanian S. Haran, Watervliet, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 27/088 (2006.01); H01L 29/45 (2006.01); H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/28088 (2013.01); H01L 21/823835 (2013.01); H01L 21/823842 (2013.01); H01L 27/088 (2013.01); H01L 29/45 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01);
Abstract

A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.


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