The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2016
Filed:
Jun. 26, 2015
Cadence Design Systems, Inc., San Jose, CA (US);
Amit Dhuria, Uttar Pradesh, IN;
Naresh Kumar, Uttar Pradesh, IN;
Prashant Sethia, Uttar Pradesh, IN;
Jeannette Sutherland, Cedar Park, TX (US);
Shashank Tripathi, Uttar Pradesh, IN;
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Abstract
A static timing analysis method for input/output modes of an integrated circuit design, that includes loading the integrated circuit design described in a hardware description language into a memory. An active zone for static timing analysis is defined, which comprises logic and interconnect between an input/output port and a selected level of sequential logic elements upstream from an input port and downstream from an output port. A description of the active zone is generated using the hardware description language. Then a static timing analysis is performed on the logic of the active zone.