The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2016
Filed:
Apr. 01, 2014
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Yen-Sen Wang, Hsinchu, TW;
Ting Yu Chen, Hsinchu, TW;
Ken-Hsien Hsieh, Taipei, TW;
Ming-Yi Lin, Hsinchu, TW;
Chen-Hung Lu, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
Some embodiments relate to a method of hierarchical layout design, comprising forming a layout of an integrated circuit (IC) according to a design rule that specifies a minimum design rule distance between a neighboring layout features within the IC. Forming the layout comprises forming first and second standard cells having first and second layout features, respectively, that about one-another so that a distance between the first and second layout features is less than the minimum design rule distance. The method further comprises configuring design rule checking (DRC) to ignore this fail. Instead, the layout is modified with an automated layout tool by merging the first and second layout features, or by removing a portion of the first or second layout feature to increase the distance between the first and second layout features to be greater than or equal to the minimum distance.