The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Aug. 05, 2015
Applicant:

Xintec Inc., Taoyuan, TW;

Inventor:

Chien-Min Lin, Taoyuan, TW;

Assignee:

XINTEC INC., Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81B 7/00 (2006.01); H01L 21/48 (2006.01); B81C 1/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
B81B 7/007 (2013.01); B81C 1/00301 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); B81B 2201/0264 (2013.01); B81B 2207/096 (2013.01); B81C 2203/0118 (2013.01);
Abstract

A method includes forming a bump on a lower surface of an interposer. A first insulation layer is formed to cover the lower surface and bump. A trench is formed extending from the lower towards an upper surface of the interposer. A polymer supporting adhesive layer is formed to surround the bump and couples between the interposer and a semiconductor chip. The semiconductor chip has at least a sensing component and a conductive pad electrically connected to the sensing component, and the bump is connected to the conductive pad. A via is formed extending from the upper towards the lower surface. A second insulation layer is formed to cover the upper surface and the via. A redistribution layer is formed on the second insulation layer and in the via. A packaging layer is formed to cover the redistribution layer and has a second opening.


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