Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer

Abstract

When forming transistors with deuterium enhanced gate dielectrics and strained channel regions, the manufacturing processes of strain-inducing dielectric material layers formed above the transistors may be employed to efficiently introduce and diffuse the deuterium to the gate dielectrics. The incorporation of deuterium into the strain-inducing dielectric material layers may be accomplished on the basis of a deposition process in which deuterium is present in the process environment during deposition. The process temperature of the deposition process may be chosen to perform—potentially in combination with further subsequently performed process steps—a sufficient diffusion of deuterium to the gate dielectrics.