The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2016

Filed:

Aug. 29, 2014
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Ganming Qin, Chandler, AZ (US);

Edouard de Frésart, Tempe, AZ (US);

Pon Sung Ku, Gilbert, AZ (US);

Michael Petras, Phoenix, AZ (US);

Moaniss Zitouni, Gilbert, AZ (US);

Dragan Zupac, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/26513 (2013.01); H01L 21/30604 (2013.01); H01L 29/063 (2013.01); H01L 29/407 (2013.01); H01L 29/4236 (2013.01); H01L 29/42364 (2013.01); H01L 29/66666 (2013.01);
Abstract

A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and second trenches extending into the semiconductor layer from a surface of the semiconductor layer, each of the first and second trenches including a corresponding gate electrode. The semiconductor device further includes a body region having a second conductivity type different than the first conductivity type and a source contact region having the first conductivity type. The body region is disposed in the semiconductor layer below the surface of the semiconductor layer and between a sidewall of the first trench and an adjacent sidewall of a second trench. The source contact region is disposed in the semiconductor layer between the body region and the surface of the semiconductor layer and extending between the sidewall of the first trench and the corresponding sidewall of the second trench.


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