The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2016

Filed:

Apr. 29, 2015
Applicant:

Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;

Inventors:

Wei-Hsuan Lee, Kaohsiung, TW;

Sung-Mao Li, Kaohsiung, TW;

Chien-Yeh Liu, Kaohsiung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/56 (2013.01); H01L 23/3157 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06544 (2013.01);
Abstract

A semiconductor package includes a substrate, a set of electrical components, a stud, a tapering electrical interconnection and a package body. The electrical components are disposed on a top surface of the substrate. A bottom surface of the stud is disposed on the top surface of the substrate. A bottom surface of the electrical interconnection is disposed at a top surface of the stud. A width of the stud is greater than or equal to a width of the bottom surface of the electrical interconnection. The package body is disposed on the top surface of the substrate, and encapsulates the electrical components, the stud and a portion of the electrical interconnection. The package body exposes a top surface of the electrical interconnection.


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