Integrated helical multi-layer inductor structures

Abstract

A chip package comprising: a chip stack comprising at least one chip; and a thermal power plane comprising at least two substantially parallel dielectric layers having conductive connectors patterned therein, the at least two dielectric layers electrically connected by vias, wherein said vias are substantially perpendicular to the at least two dielectric layers, wherein each of the vias electrically connects to a connector patterned within a dielectric layer of the at least two dielectric layers at a via connection, wherein an inductor used in supplying power to the at least one chip is formed from the vias and from connectors electrically connecting via connections on each of the at least two dielectric layers.