The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2016

Filed:

Mar. 06, 2012
Applicants:

Evan M. Fledell, Beaverton, OR (US);

Paul B. Fischer, Portland, OR (US);

Roy E. Swart, Hillsboro, OR (US);

Timothy J. Maloney, Palo Alto, CA (US);

Jack D. Pippin, Portland, OR (US);

Inventors:

Evan M. Fledell, Beaverton, OR (US);

Paul B. Fischer, Portland, OR (US);

Roy E. Swart, Hillsboro, OR (US);

Timothy J. Maloney, Palo Alto, CA (US);

Jack D. Pippin, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 9/08 (2006.01); H02H 9/02 (2006.01); G01R 1/36 (2006.01); G01R 31/28 (2006.01); G01R 1/073 (2006.01);
U.S. Cl.
CPC ...
H02H 9/02 (2013.01); G01R 1/36 (2013.01); G01R 31/2889 (2013.01); G01R 1/07385 (2013.01);
Abstract

An interposer is described to regulate the current in wafer test tooling. In one example, the interposer includes a first connection pad to couple to automated test equipment and a second connection pad to couple to a device under test. The interposer further includes an overcurrent limit circuit to connect the first and second connection pads and to disconnect the first and second connection pads when the current between the first and second connection pads is over a predetermined amount.


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