The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Dec. 14, 2012
Applicant:

Fudan University, Shanghai, CN;

Inventors:

Dongping Wu, Shanghai, CN;

Zhaoyang Pi, Shanghai, CN;

Na Zhao, Shanghai, CN;

Wei Zhang, Shanghai, CN;

Shi-Li Zhang, Stockholm, SE;

Assignee:

FUDAN UNIVERSITY, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 29/45 (2006.01); H01L 23/485 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/486 (2013.01); H01L 21/76843 (2013.01); H01L 21/76855 (2013.01); H01L 21/76883 (2013.01); H01L 21/76889 (2013.01); H01L 23/485 (2013.01); H01L 23/53271 (2013.01); H01L 29/458 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by forming vias or contact holes in an insulator layer covering the transistor and at metal silicide contact regions corresponding to the source and drain, and by filling the vias with metal-semiconductor compound. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the material in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias.


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