The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Apr. 05, 2012
Applicants:

Salvador Palanca, Folsom, CA (US);

Stephen A. Fischer, Gold River, CA (US);

Subramaniam Maiyuran, Gold River, CA (US);

Shekoufeh Qawami, El Dorado Hills, CA (US);

Inventors:

Salvador Palanca, Folsom, CA (US);

Stephen A. Fischer, Gold River, CA (US);

Subramaniam Maiyuran, Gold River, CA (US);

Shekoufeh Qawami, El Dorado Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 9/30 (2006.01); G06F 9/40 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30145 (2013.01); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/30087 (2013.01); G06F 9/3834 (2013.01); G06F 9/3836 (2013.01); G06F 9/3855 (2013.01); G06F 9/3857 (2013.01);
Abstract

A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.


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