The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2016

Filed:

Jan. 22, 2015
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Ming-Hui Chang, Tainan, TW;

Wei-Ting Wu, Tainan, TW;

Ming-Shing Chen, Tainan, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/36 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/0692 (2013.01); H01L 29/0865 (2013.01); H01L 29/0882 (2013.01); H01L 29/1095 (2013.01); H01L 29/36 (2013.01);
Abstract

A LDMOS includes a gate structure disposed on the surface of a semiconductor substrate, a source region having a first conductivity type, a drain region having the first conductivity type, an isolation region surrounding the source/drain regions, a doped region having a second conductivity type, and a base region having the second conductivity type formed in the doped region. The source/drain regions are respectively disposed on two sides of the gate structure. The doped region surrounds the isolation region, and the bottom of the doped region is deeper than the bottom of the isolation region. The base region is disposed at the surface of the semiconductor substrate.


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