The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2016

Filed:

Apr. 24, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Murshed M. Chowdhury, Schenectady, NY (US);

Brian J. Greene, Wappingers Falls, NY (US);

Arvind Kumar, Chappaqua, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/8244 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 21/324 (2006.01); H01L 21/225 (2006.01); H01L 29/417 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 21/225 (2013.01); H01L 21/324 (2013.01); H01L 29/0649 (2013.01); H01L 29/1037 (2013.01); H01L 29/1095 (2013.01); H01L 29/41783 (2013.01); H01L 29/41791 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01);
Abstract

A dummy gate structure straddling at least one semiconductor fin is formed on a substrate. Active semiconductor regions and raised active semiconductor regions may be formed. A planarization dielectric layer is formed over the at least one semiconductor fin, and the dummy gate structure is removed to provide a gate cavity. Electrical dopants in the channel region can be removed by outgassing during an anneal, thereby lowering the concentration of the electrical dopants in the channel region. Alternately or additionally, carbon can be implanted into the channel region to deactivate remaining electrical dopants in the channel region. The threshold voltage of the field effect transistor can be effectively controlled by the reduction of active electrical dopants in the channel region. A replacement gate electrode can be subsequently formed in the gate cavity.


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