logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9379059 B1

PDFFull Text
Date of Patent:
Jun. 28, 2016

Filed:

Nov. 01, 2011

Power and ground routing of integrated circuit devices with improved ir drop and chip performance

Applicants:

Ching-chung Ko, Hsinchu County, TW;

Tao Cheng, Hsinchu, TW;

Tien-yueh Liu, Hsinchu, TW;

Ta-hsi Chou, New Taipei, TW;

Peng-cheng Kao, Hsinchu, TW;

Ling-wei KE, Hsinchu County, TW;

Inventors:

Ching-Chung Ko, Hsinchu County, TW;

Tao Cheng, Hsinchu, TW;

Tien-Yueh Liu, Hsinchu, TW;

Ta-Hsi Chou, New Taipei, TW;

Peng-Cheng Kao, Hsinchu, TW;

Ling-Wei Ke, Hsinchu County, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Andy Huynh

Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 23/528 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5286 (2013.01); H01L 21/823475 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer.

Find Patent Forward Citations

Ko, Ching-Chung. (2016). Power and ground routing of integrated circuit devices with improved ir drop and chip performance (U.S. Patent No. 9379059). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9379059

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…