The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2016

Filed:

Nov. 04, 2015
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Kiwamu Sakuma, Yokkaichi, JP;

Masahiro Kiyotoshi, Yokkaichi, JP;

Shosuke Fujii, Kuwana, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 29/792 (2006.01); H01L 21/336 (2006.01); H01L 21/20 (2006.01); H01L 27/115 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11578 (2013.01); H01L 21/02233 (2013.01); H01L 21/02255 (2013.01); H01L 21/30604 (2013.01); H01L 27/11551 (2013.01);
Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first stacked layer structure including first to nsemiconductor layers (n is a natural number greater than or equal to 2) stacked in a first direction, and extending in a second direction, and first to nmemory cells provided on surfaces of the first to nsemiconductor layers facing a third direction. The imemory cell (1≦i≦n) comprises a second stacked layer structure in which a first insulating layer, a charge storage layer, a second insulating layer, and a control gate electrode are stacked. The second insulating layer has an equivalent oxide thickness smaller than that of the first insulating layer.


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