The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Mar. 26, 2014
Applicant:

Kinsus Interconnect Technology Corp., Taoyuan, TW;

Inventors:

Ting-Hao Lin, Taipei, TW;

Yu-Te Lu, Taoyuan Hsien, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/46 (2006.01); H05K 3/00 (2006.01); H05K 3/10 (2006.01); H05K 3/28 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4611 (2013.01); H05K 3/0094 (2013.01); H05K 3/10 (2013.01); H05K 3/28 (2013.01); H05K 3/3452 (2013.01); H05K 2203/06 (2013.01); H05K 2203/0723 (2013.01); H05K 2203/143 (2013.01);
Abstract

A method of manufacturing a multilayer substrate structure includes the steps of pre-treatment, pressing and post-treatment. A carrier plate provided with a circuit pattern layer is pressed against a plastic sheet. An interlayer connection pad is formed by drilling and filling the lower surface of the plastic sheet. The carrier plate, the plastic sheet, another plastic sheet and another carrier plate with a circuit pattern layer are pressed together, and then drilled/filled to form a multilayer stacked structure such that the two circuit pattern layers are indirectly and electrically connected to the interlayer connection pad, respectively. Therefore, it is possible to overcome the problem due to alignment tolerance by using the interlayer connection pad wider than alignment tolerance, and stacking the circuit layers, each having much finer line and smaller pitch.


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