The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Dec. 14, 2012
Applicant:

Spansion Llc, Sunnyvale, CA (US);

Inventors:

Shenqing Fang, Fremont, CA (US);

Chun Chen, San Jose, CA (US);

Unsoon Kim, San Jose, CA (US);

Mark Ramsbey, Sunnyvale, CA (US);

Kuo Tung Chang, Saratoga, CA (US);

Sameer Haddad, San Jose, CA (US);

James Pak, Sunnyvale, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 27/115 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66833 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/42344 (2013.01); H01L 29/792 (2013.01); H01L 21/28282 (2013.01);
Abstract

Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer.


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