The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2016
Filed:
Sep. 02, 2015
Freescale Semiconductor, Inc., Austin, TX (US);
Cheong Min Hong, Austin, TX (US);
Asanga H. Perera, West Lake Hills, TX (US);
Sung-Taeg Kang, Austin, TX (US);
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device () includes a metal gate (), an upper high-k gate dielectric layer (), a middle gate dielectric layer () formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack () formed with one or more low-k gate oxide layers (), where each DGO transistor device () includes a metal gate (), an upper high-k gate dielectric layer (), and a middle gate dielectric layer () formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device () includes a metal gate (), an upper high-k gate dielectric layer (), and a base oxide layer () formed with one or more low-k gate oxide layers.