The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Jan. 30, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY (US);

Inventors:

Hong Yu, Rexford, NY (US);

HongLiang Shen, Ballston Lake, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/76 (2006.01); H01L 27/088 (2006.01); H01L 21/70 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/16 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7855 (2013.01);
Abstract

Methods for creating uniform source/drain cavities filled with uniform levels of materials in an IC device and resulting devices are disclosed. Embodiments include forming a hard mask on an upper surface of a Si substrate, the hard mask having an opening over a STI region formed in the Si substrate and extending over adjacent portions of the Si substrate; forming low-k dielectric spacers on a lower portion of sidewalls of the opening, the spacers being formed between the sidewalls and the STI region; filling the opening with an oxide; removing the hard mask; removing an upper portion of the oxide and a portion of the low-k dielectric spacers; revealing a Si fin in the Si substrate; forming equally spaced gate electrodes, each having sidewall spacers, over the Si fin and the oxide; and forming source/drain regions in the Si fin between each pair of adjacent gate electrodes.


Find Patent Forward Citations

Loading…