The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2016
Filed:
Sep. 10, 2015
J-devices Corporation, Oita, JP;
Hiroaki Matsubara, Kanagawa, JP;
Tomoshige Chikai, Kanagawa, JP;
Kiminori Ishido, Kanagawa, JP;
Takashi Nakamura, Kanagawa, JP;
Hirokazu Honda, Kanagawa, JP;
Hiroshi Demachi, Kanagawa, JP;
Yoshikazu Kumagaya, Miyagi, JP;
Shotaro Sakumoto, Kanagawa, JP;
Shinji Watanabe, Kanagawa, JP;
Sumikazu Hosoyamada, Oita, JP;
Shingo Nakamura, Kanagawa, JP;
Takeshi Miyakoshi, Hokkaido, JP;
Toshihiro Iwasaki, Kanagawa, JP;
Michiaki Tamakawa, Kanagawa, JP;
J-DEVICES CORPORATION, Oita, JP;
Abstract
A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness.