The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2016
Filed:
Apr. 10, 2012
I-chang Shih, Tucheng, TW;
Chung-min Fu, Chungli, TW;
Ying-chou Cheng, Zhubei, TW;
Yung-fong LU, Keelung, TW;
Feng-yuan Chiu, Hsinchu, TW;
Chiu Hsiu Chen, Hsinchu County, TW;
I-Chang Shih, Tucheng, TW;
Chung-min Fu, Chungli, TW;
Ying-Chou Cheng, Zhubei, TW;
Yung-Fong Lu, Keelung, TW;
Feng-Yuan Chiu, Hsinchu, TW;
Chiu Hsiu Chen, Hsinchu County, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.