The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2016
Filed:
Dec. 22, 2015
Intel Corporation, Santa Clara, CA (US);
Paul S. Diefenbaugh, Portland, OR (US);
Robert E. Gough, Sherwood, OR (US);
Yuval Bachrach, Haifa, IL;
Mikal C. Hunsaker, El Dorado Hills, CA (US);
Rafi Ben-Tal, Yokneam, IL;
Ilan Pardo, Ramat-Hasharon, IL;
Gideon Prat, Haifa, IL;
David J. Harriman, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A system on a chip (SoC) is provided including processing cores and a root complex. The transaction requests are communicated between a root port of the root complex and a device, the root port including electrical idle (EI) exit detect circuitry and a reference clock source. The root port supports a first link state, in which the reference clock source and EI exit detect circuitry of the root port are disabled but a common mode voltage is maintained, and a second link state, in which the reference clock source and EI exit detect circuitry are disabled and the common mode voltage is not maintained. The root port transitions to the first link state based on a service latency requirement of the device being less than a threshold and to the second link state based on the service latency requirement being greater than or equal to the threshold.