The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2016
Filed:
Jul. 07, 2015
Globalfoundries Inc., Grand Cayman, KY;
Zhendong Hong, San Jose, CA (US);
Susie Tzeng, Fremont, CA (US);
Amol Joshi, Sunnyvale, CA (US);
Ashish Bodke, San Jose, CA (US);
Divya Pisharoty, Fremont, CA (US);
Usha Raghuram, Saratoga, CA (US);
Olov Karlsson, San Jose, CA (US);
Kisik Choi, Hopewell Junction, NY (US);
Salil Mujumdar, San Jose, CA (US);
Paul R. Besser, Sunnyvale, CA (US);
Jinping Liu, Ballston Lake, NY (US);
Hoon Kim, Guilderland, NY (US);
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Abstract
An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.